This invention relates to a method for creating thin, crystalline or polycrystalline layers of a material such as silicon, and more particularly to such a method that requires neither high temperature furnace cycles nor wire-sawing methods.
Thin layers of crystalline or polycrystalline silicon (<25 μm) are of tremendous technological interest for low-cost photovoltaics and other applications because silicon represents about 25% of total module cost [5]. Because the layers are thin, for these applications polycrystalline devices will also be possible. Standard wire-sawing, however, cannot achieve thicknesses this low and is very wasteful, with about half of the initially grown material lost to “saw dust” or “kerf” (a fraction that grows as thinner wafers are achieved). Economic routes to thin crystalline Si layers would have significant impact.
The dominant existing technologies for silicon wafer production include the Czochralski and Float Zone processes. In both of these manufacturing techniques, a silicon ingot is produced from a molten silicon source through a crystallization process. Subsequently, the ingots are sliced into wafers of varying diameters and thicknesses. During the slicing process, a large fraction of the as-grown material is lost as waste (known as “kerf”). In addition, wire-sawn wafers are currently limited to thicknesses of about 80-100 μm for reasons of breakage and mechanical stability. Although thinner wafers may be possible with wire-sawing in the future, the diameter of the wires is also about >100 μm as well. Because a thickness of material equal to the wire diameter is lost as kerf, thinner wafers incur larger relative losses. Because the lost material is highly purified crystalline silicon, this represents a large component of the embedded cost.
Alternative methods exist for growing crystalline silicon that avoid wire sawing, and are referred to generally as “kerfless” techniques. For example, the string ribbon and edge-defined growth techniques both pull crystalline silicon wafers directly from the melt. However, wafers grown in these techniques are thermally intensive and cannot achieve layer thicknesses much below 100 μm.
Finally, an existing perforated/porous silicon process utilizes a double-porous layer and mechanical exfoliation. However, it utilizes a high temperature process (˜1400 K) to achieve recrystallization and high-temperature epitaxial CVD growth. This decreases throughput and increases the energy intensity and cost of the process. Although it can, in principle, achieve comparably thin layers, the minimum useful device thickness will be limited by the thermal diffusion of dopants during high temperature epitaxial CVD growth.
It is therefore an object of the invention to provide a method for making thin, crystalline or polycrystalline silicon that reduces the amount of silicon wasted during prior art sawing processes. Further, it is an object to provide a method that enables layer thicknesses much thinner than possible using wire sawing methods. Yet another object of the invention is to realize desirable photovoltaic architectures including homojunction devices, monolithically integrated, all-silicon multi-junction cells, and other silicon-based devices for electricity production or photoelectroloysis.
It is a further object of the invention to directly realize thin (<1-100 μm) layers of crystalline silicon that are monocrystalline or multicrystalline with large grain size and low defect concentration.
It is yet another object of the invention to minimize thermal processing by eliminating furnace cycles.